The disclosed embodiments of the present invention relate to generating a clock signal at a transmitting end and recovering a clock signal at a receiving end, and more particularly, to a signal transmission system with a clock signal generator configured for generating a clock signal having a stepwise/smooth frequency transition and related signal transmission method thereof.
Clock signals are critical to normal operations of circuit components. When the circuit components are disposed in different chips, there is a need to make a processing result of one chip transmitted to the next chip for further processing. In addition, the clock signal used in one chip may be required to be used in the next chip for correctly dealing with the processing result generated from the preceding chip. One conventional design is to generate a clock signal at one chip (i.e., a receiving end) according to information given from a preceding chip (e.g., a transmitting end). However, when the frequency of the clock signal at the transmitting end has a significant change, the clock signal generated at the receiving end may fail to swiftly track the frequency variation of the clock signal generated at the transmitting end. Thus, the generation of the clock signal at the receiving end becomes unstable, leading to abnormal operation of the receiving end.
Taking the television (TV) video display for example, one image processing chip may be coupled to a timing controller chip, wherein the image processing chip may be utilized for processing an input video stream and generate an output video stream, and the timing controller chip may be utilized for referring to the output video stream for supplying a clock signal and image data signals synchronized with the clock signal to a display panel such as a liquid crystal display (LCD) panel. When the user changes the video source, the frame rate or the video resolution in a normal operation, the frequency of the clock signal at the transmitting end (i.e., the image processing chip) is changed accordingly. It is possible that the picture displayed on the display panel flickers because of the hardware limitation of a clock generator implemented at the receiving end (i.e., the timing controller chip). To avoid the flicker problem, the traditional method proposes terminating the transmission process between the transmitting end and the receiving end, waiting for a stable clock signal locked to a new frequency by the clock generator at the receiving end, and resuming the transmission process between the transmitting end and the receiving end after the stable clock signal with the new frequency is generated by the clock generator at the receiving end. However, in some TV testing criteria, terminating the transmission process between the transmitting end and the receiving end is not acceptable since the display panel would fail to show the on-screen display (OSD) status.
Thus, there is a need for an innovative signal transmission design which can solve the flicker problem without terminating the transmission process between the transmitting end and the receiving end.